Success Stories

Four programs. One workflow.

Most of this work is under NDA. The shape of the problem isn't. Four representative edge-AI engagements — anonymised, technically honest.

Anonymous on purpose. Specific anyway.

The decisions, the artefacts and the numbers below are real. The customer names are not. NDAs cover the brands; they do not cover the engineering.

Customer A.

Industrial vision OEM · factory inspection

Off-the-shelf SoC. Inference latency over budget; sensor lanes idle while the NPU waited on memory. Power envelope already locked by the enclosure.

What we did — profiled the workload at architecture level with DeVign; re-partitioned the data path so the ISP, NPU and DDR controller stopped fighting for the same bus.
What we did — rebuilt the SoC integration with XACT-Forge from the candidate IP set; emitted IP-XACT 1685, wired the new topology in hours.
What we did — VerifAi generated the UVM testbench, C reference model, and coverage map against the new spec — not against the legacy testbench.
Outcome — inference latency inside the per-frame budget at the same power. Verification effort: 16 person-months instead of the customer's original 80–120 estimate.

Customer B.

Multimodal edge sensing · smart camera platform

Three sensor lanes — vision, audio, IMU — feeding one fusion NPU. The integration plan was a wiring nightmare; the verification plan was a stack of unrelated testbenches.

What we did — XACT-Forge parsed every sensor IP, including two third-party blocks delivered as encrypted Verilog; emitted IP-XACT 1685 across the lot.
What we did — collapsed three legacy testbenches into a single VerifAi run: one DV plan, one coverage map, four artefacts out. Coverage measured against the spec, not the wiring.
What we did — DeVign tracked the design from architectural intent down to the register-level handshake on the fusion bus.
Outcome — first-silicon bring-up to fused inference in under three weeks. Bug escapes into post-silicon: zero on the fusion path.

Customer C.

Drone autonomy stack · FPGA → SiP → ASIC

A working FPGA prototype that wouldn't survive the BOM. Volume rising, power budget falling, customer asked the one question every founder eventually asks: when does the ASIC pay back?

What we did — modelled three migration paths in DeVign — stay on FPGA, package as SiP, full ASIC at TSMC — with honest unit-economics numbers, not slideware.
What we did — SiP first. Prototyped the data path on existing dies, proved the thermal and BOM story before committing to mask cost.
What we did — when the SiP volume cleared threshold, XACT-Forge regenerated the integration as an ASIC topology and VerifAi rebuilt the verification stack against the new spec.
Outcome — SiP shipped in two quarters. ASIC tape-out plan with a defensible payback curve. Same RTL travelled from FPGA bench to foundry sign-off.

Customer D.

Autonomous mobility · onboard inference platform

Perception, planning, safety monitor — all on one die, all on a hard latency budget. The team had RTL, sensors, and no story for sign-off.

What we did — architecture exploration in DeVign at the abstraction level the budget actually lived at; settled the perception/planner partition before a single new line of RTL.
What we did — XACT-Forge regenerated the SoC integration each time the partition moved; the team stopped re-drawing block diagrams in the second week.
What we did — VerifAi authored the verification plan including the safety-monitor lock-step coverage. Software bring-up started on the virtual platform before silicon came back.
Outcome — end-to-end latency inside budget on first silicon. Software team had a working bring-up image waiting at the door.

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