ArcASIC
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Technology

Built for the edge. Co-optimised end to end.

Edge AI silicon lives or dies on the joints — sensors, pre-processing, model execution, memory, interconnect, software, physical implementation. We ship the platform that moves those joints together. Three named tools at the core. Architecture exploration, virtual platforms, and sensor data-path tuning around them.

01

XACT-Forge.

IP-XACT generator

Automated SoC integration. Reads any IP — soft, hard, third-party, in-house. Generates IP-XACT that downstream tools and your integration team can actually use. Hand-writing it takes weeks; this takes minutes.

  • Parses Verilog, SystemVerilog, and vendor packages into canonical descriptions.
  • Infers bus types, address maps, and clock/reset crossings — surfaces what it can't infer for you to confirm.
  • Emits IP-XACT 1685 — round-trips to and from existing flows without losing fidelity.
  • Integration stays a human decision. XACT-Forge just delivers the parts pre-labelled, so wiring them is hours, not weeks.
CPU · 4× NoC · AXI4 L3 $ DMA DDR · PHY PCIe Gen5 APB · cfg NPU JTAG 14 ports · 132 nets 22 ports · 248 nets 8 ports · 96 nets 6 ports · 64 nets 18 ports · 184 nets 10 ports · 112 nets 4 ports · 24 nets 16 ports · 156 nets 3 ports · 12 nets $ arc xact-forge --infer soc.v ✓ 9 ip · 121 ports · 1,028 nets · ip-xact emitted
SPEC.PDF verifai synthesis UVM · TB reusable testbench C · REF reference model TESTS · n directed + random DV · PLAN coverage map one document in · four artefacts out · reproducible
02

VerifAi.

Agentic verification synthesis

Verification acceleration. Drop in a spec. VerifAi returns a working UVM testbench, a C reference model, a body of testcases, and a verification plan — every artefact wired to the same intent.

  • Reads natural-language specs, registers, and timing diagrams.
  • Generates UVM that compiles on first run — agents, sequences, scoreboards.
  • Writes a C reference model — the golden behaviour your scoreboard checks against, at the granularity that makes sense for the block.
  • The plan is not paperwork; it is the source of truth the tests are derived from.
03

DeVign.

RTL design intelligence · IDE

Architecture exploration in the workbench that knows your project. DeVign opens every block at whichever abstraction you need — architectural intent, microarchitecture, register-level, RTL — and a proprietary AI stack writes the tests as you go. Software starts before silicon. From the day the spec is written to the day the chip retires, the same context follows the silicon.

01

Proprietary AI stack.

Built in-house for verification, not generic code. The model has read your repo, your specs, your past failures. Every suggestion is project-specific.

02

Abstraction slider.

Slide a block between architectural intent, microarchitecture, register-level, and RTL — without switching tools or losing context.

03

Inline test authoring.

The assistant writes directed tests, sanity testbenches, and assertions for the block on your screen — not the generic one.

04

Project memory.

DeVign remembers every commit, every wave, every failure. The longer you work together, the sharper the suggestions become.

05

System verification.

When the blocks are done, DeVign stitches them. System-level testbenches and overnight regressions run from the same knowledge graph.

06

Day one to retirement.

The same context follows the chip through spec, RTL, tape-out, silicon bring-up, field deployment, and end-of-life. We are still there.

soc_top.v npu_core.sv ● noc_axi.sv tb_npu.sv devign · v0.4 ● live HIERARCHY ▾ soc_top ▾ cpu_cluster core[0..3] l2_cache ▾ npu_core ▾ pe_array ● pe[0..63] router_mesh sram_bank ctl_fsm ▸ noc_axi ▸ dma_engine ▸ pcie_top ▸ ddr_phy ▸ jtag_tap VIEW · NPU_CORE.PE_ARRAY pe[2,3] · coverage hole branch B unhit · 0 fires REGRESSION · NIGHTLY 0427 cpu_basic 100% npu_smoke 95% noc_stress 76% dma_full 100% pcie_train 39% · fail ASSISTANT YOU write a directed test for the pe[2,3] coverage hole. DEVIGN Wrote tb/npu/pe_2_3.sv · 18 cycles · weight=0x9a4 · hits branch B on cycle 11 // covers npu_pe.sv:142 if (state == ST_RETRY && weight[6] && !stall_i) next_state = ST_ISSUE; RUN TEST EXPLAIN MORE drafting follow-up test ● project loaded · 184 blocks · 12,420 nets · sim ready regression running · 22m 41s
Across the stack

Two more capabilities. Same platform.

— 04

Virtual platform enablement.

Boot the SoC before the SoC exists. DeVign drives a virtual platform from the same model the architects sign off — drivers, firmware and stack come up against it. Software starts before silicon.

— 05

Sensor & data-path optimisation.

The first millimetre of the data path decides the rest of the chip. We co-design sensor interfaces, pre-processing and on-die memory against the model — bandwidth, precision and latency budgets settled before RTL freezes.

— 06

Architecture exploration.

Try the block at intent before you write a line of RTL. DeVign keeps the same context across abstraction levels, so the trade-off you settle above the gate is the one the silicon inherits.

Migration

SiP first. ASIC when the unit economics agree.

— 01

Validate on FPGA.

Architecture and software prove themselves on programmable silicon. The platform feeds the same RTL into the FPGA as into the ASIC flow — no fork.

— 02

Ship as SiP.

Package known-good die with the accelerator. Early units in the field, real telemetry back, no mask set committed.

— 03

Commit to ASIC.

When workload and volume justify the mask set, the same architecture goes monolithic. Cost, power and area land where the model promised.

How they fit

Three tools. One arc.

Each technology stands on its own. XACT-Forge is useful the moment you have an SoC and a deadline. VerifAi earns its keep the first time a spec lands on your desk. DeVign is what happens when the same engine is working on every step at once — the topology it knows, the testbench it writes, the regression it owns.

Read it bottom-up if you want the order they were built. Read it top-down if you want the order a chip lives through.

Outcomes

What this means for customers. Numbers, not adjectives.

— 01

Faster decisions.

Architectural tradeoffs settled above RTL. Days, not quarters.

— 02

Lower integration friction.

IP-XACT out of XACT-Forge. Wiring is hours, not weeks.

— 03

Verification that keeps up.

VerifAi turns the spec into a testbench, a reference model and a plan. 16 person-months replaces 80–120.

— 04

Software ready early.

Virtual platforms boot the stack before the chip lands. Bring-up starts the day silicon does.

— 05

Hardware shaped to the workload.

Sensor, memory and compute co-tuned against the actual model — not a generic SoC template.

— 06

Prototype to production.

FPGA, SiP, ASIC — one architecture across all three stages. No re-architecting at handover.

Bring a real block.
We'll parse it on the call.

One subsystem, one hour. Engineering attends.

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